(1) Field of the Invention
The present invention relates to a method of chemical mechanical polishing and, more particularly, a method of chemical mechanical polishing using an oxide slurry and a polish stop layer to polish both polysilicon and oxide simultaneously in the fabrication of an integrated circuit device.
(2) Description of the Prior Art
Dynamic random access memory (DRAM) devices are widely used in the art. The formation of polysilicon cylindrical capacitors is becoming important. Often, a polysilicon plug is used to form the bottom portion of the cylindrical capacitor. Chemical mechanical polishing (CMP) is routinely used to planarize the polysilicon plugs. However, this demands a polysilicon slurry and may demand a dedicated polisher for polysilicon. It would simplify the process to use an oxide slurry for CMP of the polysilicon plug. Oxide slurry easily removes polysilicon as well. The drawback to this idea is that the oxide slurry easily removes both the polysilicon and the inter-poly oxide (IPO) leading to uncontrollable depth of the polysilicon plug and uncontrollable IPO thickness. It is suggested to employ a polish stop layer before patterning of the polysilicon plug. This would allow polishing of the polysilicon and oxide using an oxide slurry but without polishing away the IPO.
Polish stop layers have been widely used in the art. For example, U.S. Pat. No. 5,759,917 to Grover et al discloses an oxide CMP process using a silicon nitride stop layer to form shallow trench isolation. U.S. Pat. No. 5,229,326 to Dennison et al teaches a poly plug process in which the IPO layer is first subjected to CMP, then polysilicon is deposited and CMP to form poly plugs. This process requires two CMP steps and does not use a stop layer. U.S. Pat. No. 5,700,706 to Juengling teaches a simultaneous CMP of polysilicon and BPSG, but does not use a stop layer.